SB4002A is a universal PCI Target Controller that supports PCI Spec V2.3. If you open the case of a PC and look inside, you'll notice several white connectors; these are the interface points that expose the PCI bus to add-on hardware. Using the PCI bus signals provided through these connectors, users can add functionality that isn't built into the PC, and PCI cards (such as VGA cards or internal modems) are exactly what provide that functionality. Developing a PCI card that properly interfaces with the PCI bus typically requires either a highly skilled engineer or a chip that already has the desired functionality built on top of an existing PCI bus interface. SB4002A is a chip that makes it possible to interface general-purpose I/O semiconductors or memory devices, which cannot connect to the PCI bus on their own, with the PCI bus. I/O semiconductors and memory devices with conventional input/output structures are commonly referred to in the industry as Legacy Devices. SB4002A is a universal chip designed to bridge the PCI bus and these Legacy Devices. SystemBase has spent years developing its own PCI Target Interface Core in-house and has incorporated it into our products to ensure proven reliability. SB4002A is the product that makes this core accessible to general developers building PCI bus products, and it is Korea's first and only serial semiconductor of its kind. Using SB4002A shortens development time and simplifies the development process, and our technical support makes development even easier. Notably, while competing chips support a PCI Target Interface operating speed of only 33MHz, SB4002A supports speeds of up to 66MHz — twice as fast — making it ideal for developing products that require high-speed operation.
SB4002A offers a wide range of advanced features that can be applied across many different fields. These features are easy and straightforward to implement, enabling powerful, robust designs. The capabilities outlined below demonstrate the unique strengths that SB4002A brings to a design. For further details, please refer to the SB4002A datasheet.
Conventional PCI interface chips operate at only 33MHz. SB4002A, however, operates at 66MHz, giving designers the flexibility to choose between 33MHz and 66MHz configurations when upgrading. Even at these higher speeds, the signals remain stable and support data transfer rates of up to 264MBytes per second, making SB4002A significantly faster than competing chips.
The PCI bus operates in Little Endian by default, since the peripheral devices connected to it are designed to support Little Endian. SB4002A provides built-in conversion between Little Endian and Big Endian data.
SB4002A supports five base address registers covering both memory and I/O space. Each region has its own chip select (CS) signal, and five interrupt lines are provided as well, giving developers the flexibility to allocate address space as needed. This capability is demonstrated through the UART, memory, I/O port, and PCI Target Adapter Card reference designs included with SB4002A.
SB4002A supports both real-time processing and delayed transactions. With real-time processing, data is transferred over the PCI bus and delivered to the peripheral bus within the same PCI bus transfer cycle. Delayed transactions, on the other hand, are used when a peripheral device operates at a slower speed: the request is first issued through one PCI bus cycle, and the corresponding response is then completed through a separate PCI bus cycle.
SB4002A supports PCI Power Management Interface version 1.1.
CompactPCI is an industrial PCI bus standard defined by the PICMG organization for use in industrial computers built around the standard PCI bus. The specification adopts the same bus protocol as the standard PCI bus, but without certain electrical and physical characteristics. The Hot Swap feature defined within the CompactPCI specification was designed to further strengthen industrial CompactPCI systems, allowing CompactPCI boards to be inserted into or removed from a CompactPCI slot on an industrial computer without powering down the system. SB4002A complies with CompactPCI Hot Swap Specification 1.0.
SB4002A provides 7 GPIO pins. To control these 7 GPIOs, SB4002A includes a GPIO enable register and an I/O register.
| Features | Compliant with PCI Local Bus Specification 2.3 Supports PCI burst transfer speeds of up to 264MByte/sec (32-bit bus @ 66MHz) Supports an ISA-like local system bus, with transaction speeds of up to 66MHz Selectable local bus data width (8-bit, 16-bit, or 32-bit) with Little or Big Endian selection Supports PCI Power Management 1.1 Supports CompactPCI and CompactPCI Hot Swap Supports up to 5 local address regions (configurable as I/O or memory space) Provides 5 chip select signals and interrupt lines Adjustable local bus read and write timing Delayed read and write functionality using an internal PCI FIFO PCI configuration header data can be loaded from an external serial ROM Electrically compliant with PCI Local Bus Specification 3.0 (compatible with both PCI and PCI-X buses) 3.3V operation, 5V signal input tolerant 176-pin TQFP package |
| Application Areas | A wide range of PCI target adapter cards Digital I/O and analog I/O cards Storage cards Data control cards Serial multiport cards |
Click the button below to go to the resource center, where you can download related materials such as manuals, drivers, and utilities.
DownloadSB4002A is a universal PCI Target Controller that supports PCI Spec V2.3. If you open the case of a PC and look inside, you'll notice several white connectors; these are the interface points that expose the PCI bus to add-on hardware. Using the PCI bus signals provided through these connectors, users can add functionality that isn't built into the PC, and PCI cards (such as VGA cards or internal modems) are exactly what provide that functionality. Developing a PCI card that properly interfaces with the PCI bus typically requires either a highly skilled engineer or a chip that already has the desired functionality built on top of an existing PCI bus interface. SB4002A is a chip that makes it possible to interface general-purpose I/O semiconductors or memory devices, which cannot connect to the PCI bus on their own, with the PCI bus. I/O semiconductors and memory devices with conventional input/output structures are commonly referred to in the industry as Legacy Devices. SB4002A is a universal chip designed to bridge the PCI bus and these Legacy Devices. SystemBase has spent years developing its own PCI Target Interface Core in-house and has incorporated it into our products to ensure proven reliability. SB4002A is the product that makes this core accessible to general developers building PCI bus products, and it is Korea's first and only serial semiconductor of its kind. Using SB4002A shortens development time and simplifies the development process, and our technical support makes development even easier. Notably, while competing chips support a PCI Target Interface operating speed of only 33MHz, SB4002A supports speeds of up to 66MHz — twice as fast — making it ideal for developing products that require high-speed operation.
SB4002A offers a wide range of advanced features that can be applied across many different fields. These features are easy and straightforward to implement, enabling powerful, robust designs. The capabilities outlined below demonstrate the unique strengths that SB4002A brings to a design. For further details, please refer to the SB4002A datasheet.
Conventional PCI interface chips operate at only 33MHz. SB4002A, however, operates at 66MHz, giving designers the flexibility to choose between 33MHz and 66MHz configurations when upgrading. Even at these higher speeds, the signals remain stable and support data transfer rates of up to 264MBytes per second, making SB4002A significantly faster than competing chips.
The PCI bus operates in Little Endian by default, since the peripheral devices connected to it are designed to support Little Endian. SB4002A provides built-in conversion between Little Endian and Big Endian data.
SB4002A supports five base address registers covering both memory and I/O space. Each region has its own chip select (CS) signal, and five interrupt lines are provided as well, giving developers the flexibility to allocate address space as needed. This capability is demonstrated through the UART, memory, I/O port, and PCI Target Adapter Card reference designs included with SB4002A.
SB4002A supports both real-time processing and delayed transactions. With real-time processing, data is transferred over the PCI bus and delivered to the peripheral bus within the same PCI bus transfer cycle. Delayed transactions, on the other hand, are used when a peripheral device operates at a slower speed: the request is first issued through one PCI bus cycle, and the corresponding response is then completed through a separate PCI bus cycle.
SB4002A supports PCI Power Management Interface version 1.1.
CompactPCI is an industrial PCI bus standard defined by the PICMG organization for use in industrial computers built around the standard PCI bus. The specification adopts the same bus protocol as the standard PCI bus, but without certain electrical and physical characteristics. The Hot Swap feature defined within the CompactPCI specification was designed to further strengthen industrial CompactPCI systems, allowing CompactPCI boards to be inserted into or removed from a CompactPCI slot on an industrial computer without powering down the system. SB4002A complies with CompactPCI Hot Swap Specification 1.0.
SB4002A provides 7 GPIO pins. To control these 7 GPIOs, SB4002A includes a GPIO enable register and an I/O register.
| Features | Compliant with PCI Local Bus Specification 2.3 Supports PCI burst transfer speeds of up to 264MByte/sec (32-bit bus @ 66MHz) Supports an ISA-like local system bus, with transaction speeds of up to 66MHz Selectable local bus data width (8-bit, 16-bit, or 32-bit) with Little or Big Endian selection Supports PCI Power Management 1.1 Supports CompactPCI and CompactPCI Hot Swap Supports up to 5 local address regions (configurable as I/O or memory space) Provides 5 chip select signals and interrupt lines Adjustable local bus read and write timing Delayed read and write functionality using an internal PCI FIFO PCI configuration header data can be loaded from an external serial ROM Electrically compliant with PCI Local Bus Specification 3.0 (compatible with both PCI and PCI-X buses) 3.3V operation, 5V signal input tolerant 176-pin TQFP package |
| Application Areas | A wide range of PCI target adapter cards Digital I/O and analog I/O cards Storage cards Data control cards Serial multiport cards |
Click the button below to go to the resource center, where you can download related materials such as manuals, drivers, and utilities.
Download
